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Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture , readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.

Tabla de contenidos provista por Syndetics

• Preface(p. xvii)
• Features(p. xviii)
• Online Supplements(p. xix)
• How to Use the Software Tools in a Course(p. xix)
• Labs(p. xx)
• Bugs(p. xxi)
• Acknowledgments(p. xxi)
• Chapter 1 From Zero to One(p. 3)
• 1.1 The Game Plan(p. 3)
• 1.2 The Art of Managing Complexity(p. 4)
• 1.2.1 Abstraction(p. 4)
• 1.2.2 Discipline(p. 5)
• 1.2.3 The Three -Y's(p. 6)
• 1.3 The Digital Abstraction(p. 7)
• 1.4 Number Systems(p. 9)
• 1.4.1 Decimal Numbers(p. 9)
• 1.4.2 Binary Numbers(p. 9)
• 1.4.3 Hexadecimal Numbers(p. 11)
• 1.4.4 Bytes, Nibbles, and All That Jazz(p. 13)
• 1.4.5 Binary Addition(p. 14)
• 1.4.6 Signed Binary Numbers(p. 15)
• 1.5 Logic Gates(p. 19)
• 1.5.1 NOT Gate(p. 20)
• 1.5.2 Buffer(p. 20)
• 1.5.3 AND Gate(p. 20)
• 1.5.4 OR Gate(p. 21)
• 1.5.5 Other Two-Input Gates(p. 21)
• 1.5.6 Multiple-Input Gates(p. 21)
• 1.6 Beneath the Digital Abstraction(p. 22)
• 1.6.1 Supply Voltage(p. 22)
• 1.6.2 Logic Levels(p. 22)
• 1.6.3 Noise Margins(p. 23)
• 1.6.4 DC Transfer Characteristics(p. 23)
• 1.6.5 The Static Discipline(p. 24)
• 1.7 CMOS Transistors(p. 26)
• 1.7.1 Semiconductors(p. 27)
• 1.7.2 Diodes(p. 27)
• 1.7.3 Capacitors(p. 28)
• 1.7.4 nMOS and pMOS Transistors(p. 28)
• 1.7.5 CMOS NOT Gate(p. 31)
• 1.7.6 Other CMOS Logic Gates(p. 31)
• 1.7.7 Transmission Gates(p. 33)
• 1.7.8 Pseudo-nMOS Logic(p. 33)
• 1.8 Power Consumption(p. 34)
• 1.9 Summary and a Look Ahead(p. 35)
• Exercises(p. 37)
• Interview Questions(p. 48)
• Chapter 2 Combinational Logic Design(p. 51)
• 2.1 Introduction(p. 51)
• 2.2 Boolean Equations(p. 54)
• 2.2.1 Terminology(p. 54)
• 2.2.2 Sum-of-Products Form(p. 54)
• 2.2.3 Product-of-Sums Form(p. 56)
• 2.3 Boolean Algebra(p. 56)
• 2.3.1 Axioms(p. 57)
• 2.3.2 Theorems of One Variable(p. 57)
• 2.3.3 Theorems of Several Variables(p. 58)
• 2.3.4 The Truth Behind It All(p. 60)
• 2.3.5 Simplifying Equations(p. 61)
• 2.4 From Logic to Gates(p. 62)
• 2.5 Multilevel Combinational Logic(p. 65)
• 2.5.1 Hardware Reduction(p. 66)
• 2.5.2 Bubble Pushing(p. 67)
• 2.6 X's and Z's, Oh My(p. 69)
• 2.6.1 Illegal Value: X(p. 69)
• 2.6.2 Floating Value: Z(p. 70)
• 2.7 Karnaugh Maps(p. 71)
• 2.7.1 Circular Thinking(p. 73)
• 2.7.2 Logic Minimization with K-Maps(p. 73)
• 2.7.3 Don't Cares(p. 77)
• 2.7.4 The Big Picture(p. 78)
• 2.8 Combinational Building Blocks(p. 79)
• 2.8.1 Multiplexers(p. 79)
• 2.8.2 Decoders(p. 82)
• 2.9 Timing(p. 84)
• 2.9.1 Propagation and Contamination Delay(p. 84)
• 2.9.2 Glitches(p. 88)
• 2.10 Summary(p. 91)
• Exercises(p. 93)
• Interview Questions(p. 100)
• Chapter 3 Sequential Logic Design(p. 103)
• 3.1 Introduction(p. 103)
• 3.2 Latches and Flip-Flops(p. 103)
• 3.2.1 SR Latch(p. 105)
• 3.2.2 D Latch(p. 107)
• 3.2.3 D Flip-Plop(p. 108)
• 3.2.4 Register(p. 108)
• 3.2.5 Enabled Flip-Flop(p. 109)
• 3.2.6 Resettable Flip-Flop(p. 110)
• 3.2.7 Transistor-Level Latch and Flip-Flop Designs(p. 110)
• 3.2.8 Putting It All Together(p. 112)
• 3.3 Synchronous Logic Design(p. 113)
• 3.3.1 Some Problematic Circuits(p. 113)
• 3.3.2 Synchronous Sequential Circuits(p. 114)
• 3.3.3 Synchronous and Asynchronous Circuits(p. 116)
• 3.4 Finite State Machines(p. 117)
• 3.4.1 FSM Design Example(p. 117)
• 3.4.2 State Encodings(p. 123)
• 3.4.3 Moore and Mealy Machines(p. 126)
• 3.4.4 Factoring State Machines(p. 129)
• 3.4.5 FSM Review(p. 132)
• 3.5 Timing of Sequential Logic(p. 133)
• 3.5.1 The Dynamic Discipline(p. 134)
• 3.5.2 System Tinting(p. 135)
• 3.5.3 Clock Skew(p. 140)
• 3.5.4 Metastability(p. 143)
• 3.5.5 Synchronizers(p. 144)
• 3.5.6 Derivation of Resolution Time(p. 146)
• 3.6 Parallelism(p. 149)
• 3.7 Summary(p. 153)
• Exercises(p. 155)
• Interview Questions(p. 165)
• Chapter 4 Hardware Description Languages(p. 167)
• 4.1 Introduction(p. 167)
• 4.1.1 Modules(p. 167)
• 4.1.2 Language Origins(p. 168)
• 4.1.3 Simulation and Synthesis(p. 169)
• 4.2 Combinational Logic(p. 171)
• 4.2.1 Bitwise Operators(p. 171)
• 4.2.2 Comments and White Space(p. 174)
• 4.2.3 Reduction Operators(p. 174)
• 4.2.4 Conditional Assignment(p. 175)
• 4.2.5 Internal Variables(p. 176)
• 4.2.6 Precedence(p. 178)
• 4.2.7 Numbers(p. 179)
• 4.2.8 Z's and X's(p. 179)
• 4.2.9 Bit Swizzling(p. 182)
• 4.2.10 Delays(p. 182)
• 4.2.11 VHDL Libraries and Types(p. 183)
• 4.3 Structural Modeling(p. 185)
• 4.4 Sequential Logic(p. 190)
• 4.4.1 Registers(p. 190)
• 4.4.2 Resettable Registers(p. 191)
• 4.4.3 Enabled Registers(p. 193)
• 4.4.4 Multiple Registers(p. 194)
• 4.4.5 Latches(p. 195)
• 4.5 More Combinational Logic(p. 195)
• 4.5.1 Case Statements(p. 198)
• 4.5.2 If Statements(p. 199)
• 4.5.3 Verilog casez(p. 201)
• 4.5.4 Blocking and Nonblocking Assignments(p. 201)
• 4.6 Finite State Machines(p. 206)
• 4.7 Parameterized Modules(p. 211)
• 4.8 Testbenches(p. 214)
• 4.9 Summary(p. 218)
• Exercises(p. 219)
• Interview Questions(p. 230)
• Chapter 5 Digital Building Blocks(p. 233)
• 5.1 Introduction(p. 233)
• 5.2 Arithmetic Circuits(p. 233)
• 5.2.1 Addition(p. 233)
• 5.2.2 Subtraction(p. 240)
• 5.2.3 Comparators(p. 240)
• 5.2.4 ALU(p. 242)
• 5.2.5 Shifters and Rotators(p. 244)
• 5.2.6 Multiplication(p. 246)
• 5.2.7 Division(p. 247)
• 5.2.8 Further Reading(p. 248)
• 5.3 Number Systems(p. 249)
• 5.3.1 Fixed-Point Number Systems(p. 249)
• 5.3.2 Floating-Point Number Systems(p. 250)
• 5.4 Sequential Building Blocks(p. 254)
• 5.4.1 Counters(p. 254)
• 5.4.2 Shift Registers(p. 255)
• 5.5 Memory Arrays(p. 257)
• 5.5.1 Overview(p. 257)
• 5.5.2 Dynamic Random Access Memory(p. 260)
• 5.5.3 Static Random Access Memory(p. 260)
• 5.5.4 Area and Delay(p. 261)
• 5.5.5 Register Files(p. 261)
• 5.5.6 Read Only Memory(p. 262)
• 5.5.7 Logic Using Memory Arrays(p. 264)
• 5.5.8 Memory HDL(p. 264)
• 5.6 Logic Arrays(p. 266)
• 5.6.1 Programmable Logic Array(p. 266)
• 5.6.2 Field Programmable Gate Array(p. 268)
• 5.6.3 Array Implementations(p. 273)
• 5.7 Summary(p. 274)
• Exercises(p. 276)
• Interview Questions(p. 286)
• Chapter 6 Architecture(p. 289)
• 6.1 Introduction(p. 289)
• 6.2 Assembly Language(p. 290)
• 6.2.1 Instructions(p. 290)
• 6.2.2 Operands: Registers, Memory, and Constants(p. 292)
• 6.3 Machine Language(p. 299)
• 6.3.1 R-type Instructions(p. 299)
• 6.3.2 I-type Instructions(p. 301)
• 6.3.3 J-type Instructions(p. 302)
• 6.3.4 Interpreting Machine Language Code(p. 302)
• 6.3.5 The Power of the Stored Program(p. 303)
• 6.4 Programming(p. 304)
• 6.4.1 Arithmetic/Logical Instructions(p. 304)
• 6.4.2 Branching(p. 308)
• 6.4.3 Conditional Statements(p. 310)
• 6.4.4 Getting Loopy(p. 311)
• 6.4.5 Arrays(p. 314)
• 6.4.6 Procedure Calls(p. 319)
• 6.5 Addressing Modes(p. 327)
• 6.6 Lights, Camera, Action: Compiling, Assembling, and Loading(p. 330)
• 6.6.1 The Memory Map(p. 330)
• 6.6.2 Translating and Starting a Program(p. 331)
• 6.7 Odds and Ends(p. 336)
• 6.7.1 Pseudoinstructions(p. 336)
• 6.7.2 Exceptions(p. 337)
• 6.7.3 Signed and Unsigned Instructions(p. 338)
• 6.7.4 Floating-Point Instructions(p. 340)
• 6.8 Real-World Perspective: IA-32 Architecture(p. 341)
• 6.8.1 IA-32 Registers(p. 342)
• 6.8.2 IA-32 Operands(p. 342)
• 6.8.3 Status Flags(p. 344)
• 6.8.4 IA-32 Instructions(p. 344)
• 6.8.5 IA-32 Instruction Encoding(p. 346)
• 6.8.6 Other IA-32 Peculiarities(p. 348)
• 6.8.7 The Big Picture(p. 349)
• 6.9 Summary(p. 349)
• Exercises(p. 351)
• Interview Questions(p. 361)
• Chapter 7 Microarchitecture(p. 363)
• 7.1 Introduction(p. 363)
• 7.1.1 Architectural State and Instruction Set(p. 363)
• 7.1.2 Design Process(p. 364)
• 7.1.3 MIPS Microarchitectures(p. 366)
• 7.2 Performance Analysis(p. 366)
• 7.3 Single-Cycle Processor(p. 368)
• 7.3.1 Single-Cycle Datapath(p. 368)
• 7.3.2 Single-Cycle Control(p. 374)
• 7.3.3 More Instructions(p. 377)
• 7.3.4 Performance Analysis(p. 380)
• 7.4 Multicycle Processor(p. 381)
• 7.4.1 Multicycle Datapath(p. 382)
• 7.4.2 Multicycle Control(p. 388)
• 7.4.3 More Instructions(p. 395)
• 7.4.4 Performance Analysis(p. 397)
• 7.5 Pipelined Processor(p. 401)
• 7.5.1 Pipelined Datapath(p. 404)
• 7.5.2 Pipelined Control(p. 405)
• 7.5.3 Hazards(p. 406)
• 7.5.4 More Instructions(p. 418)
• 7.5.5 Performance Analysis(p. 418)
• 7.6 HDL Representation(p. 421)
• 7.6.1 Single-Cycle Processor(p. 422)
• 7.6.2 Generic Building Blocks(p. 426)
• 7.6.3 Testbench(p. 428)
• 7.7 Exceptions(p. 431)
• 7.8 Advanced Microarchitecture(p. 435)
• 7.8.1 Deep Pipelines(p. 435)
• 7.8.2 Branch Prediction(p. 437)
• 7.8.3 Superscalar Processor(p. 438)
• 7.8.4 Out-of-Order Processor(p. 441)
• 7.8.5 Register Renaming(p. 443)
• 7.8.6 Single Instruction Multiple Data(p. 445)
• 7.8.7 Multithreading(p. 446)
• 7.8.8 Multiprocessors(p. 447)
• 7.9 Real-World Perspective: IA-32 Microarchitecture(p. 447)
• 7.10 Summary(p. 453)
• Exercises(p. 455)
• Interview Questions(p. 461)
• Chapter 8 Memory Systems(p. 463)
• 8.1 Introduction(p. 463)
• 8.2 Memory System Performance Analysis(p. 467)
• 8.3 Caches(p. 468)
• 8.3.1 What Data Is Held in the Cache?(p. 469)
• 8.3.2 How Is the Data Found?(p. 470)
• 8.3.3 What Data Is Replaced?(p. 478)
• 8.3.4 Advanced Cache Design(p. 479)
• 8.3.5 The Evolution of MIPS Caches(p. 483)
• 8.4 Virtual Memory(p. 484)
• 8.4.1 Address Translation(p. 486)
• 8.4.2 The Page Table(p. 488)
• 8.4.3 The Translation Lookaside Buffer(p. 490)
• 8.4.4 Memory Protection(p. 491)
• 8.4.5 Replacement Policies(p. 492)
• 8.4.6 Multilevel Page Tables(p. 492)
• 8.5 Memory-Mapped I/O(p. 494)
• 8.6 Real-World Perspective: IA-32 Memory and I/O Systems(p. 499)
• 8.6.1 IA-32 Cache Systems(p. 499)
• 8.6.2 IA-32 Virtual Memory(p. 501)
• 8.6.3 IA-32 Programmed I/O(p. 502)
• 8.7 Summary(p. 502)
• Exercises(p. 504)
• Interview Questions(p. 512)
• Appendix A Digital System Implementation(p. 515)
• A.1 Introduction(p. 515)
• A.2 74xx Logic(p. 515)
• A.2.1 Logic Gates(p. 516)
• A.2.2 Other Functions(p. 516)
• A.3 Programmable Logic(p. 516)
• A.3.1 PROMs(p. 516)
• A.3.2 PLAs(p. 520)
• A.3.3 FPGAs(p. 521)
• A.4 Application-Specific Integrated Circuits(p. 523)
• A.5 Data Sheets(p. 523)
• A.6 Logic Families(p. 529)
• A.7 Packaging and Assembly(p. 531)
• A.8 Transmission lines(p. 534)
• A.8.1 Matched Termination(p. 536)
• A.8.2 Open Termination(p. 538)
• A.8.3 Short Termination(p. 539)
• A.8.4 Mismatched Termination(p. 539)
• A.8.5 When to Use Transmission Line Models(p. 542)
• A.8.6 Proper Transmission Line Terminations(p. 542)
• A.8.7 Derivation of Z[subscript 0](p. 544)
• A.8.8 Derivation of the Reflection Coefficient(p. 545)
• A.8.9 Putting It All Together(p. 546)
• A.9 Economics(p. 547)
• Appendix B MIPS Instructions(p. 551)
• Further Reading(p. 555)
• Index(p. 557)

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