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Rapid Prototyping of Digital Systems, Second Edition provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic.
Design engineers working in industry will also want to consider this book for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, especially if they have not had previous experience with the new and rapidly evolving technology.
Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy-to-use input and output functions were developed for this book to help the reader get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis.
A coupon is included with the text for purchase of the new UP 1X board. The additional logic and memory in the UP 1X's FLEX 10K70 is useful on larger design projects such as computers and video games.
The second edition includes an update chapter on programmable logic, new robot sensors and projects, optional Verilog examples, and a meta assembler which can be used to develop assemble language programs for the computer designs in Chapters 8 and 13.

Tabla de contenidos provista por Syndetics

• 1 Tutorial I: The 15 Minute Design(p. 2)
• 1.1 Design Entry using the Graphic Editor(p. 6)
• 1.2 Compiling the Design(p. 9)
• 1.3 Simulation of the Design(p. 10)
• 1.4 Downloading Your Design to the UP 1 or UP 1X Board(p. 12)
• 1.5 The 10 Minute VHDL Entry Tutorial(p. 14)
• 1.6 Compiling the VHDL Design(p. 17)
• 1.7 The 10 Minute Verilog Entry Tutorial(p. 17)
• 1.8 Compiling the Verilog Design(p. 21)
• 1.9 Timing Analysis(p. 22)
• 1.10 The Floorplan Editor(p. 23)
• 1.11 Symbols and Hierarchy(p. 24)
• 1.12 Functional Simulation(p. 24)
• 1.13 For additional information(p. 25)
• 1.14 Laboratory Exercises(p. 25)
• 2 The Altera UP 1 and UP 1X CPLD Boards(p. 30)
• 2.1 Programming Jumpers(p. 31)
• 2.2 MAX 7000 Device and UP 1 I/O Features(p. 31)
• 2.3 MAX and FLEX Seven-segment LED Displays(p. 31)
• 2.4 FLEX 10K Device and UP 1 I/O Features(p. 34)
• 2.5 Obtaining a UP 1 or UP 1X Board and Power Supply(p. 36)
• 3 Programmable Logic Technology(p. 38)
• 3.1 CPLDs and FPGAs(p. 41)
• 3.2 Altera MAX 7000S Architecture--A Product Term CPLD Device(p. 42)
• 3.3 Altera FLEX 10K Architecture--A Look-Up Table CPLD Device(p. 43)
• 3.4 Xilinx 4000 Architecture--A Look-Up Table FPGA Device(p. 47)
• 3.5 Computer Aided Design Tools for Programmable Logic(p. 49)
• 3.6 Next Generation FPLD CAD tools(p. 50)
• 3.7 Applications of FPLDs(p. 50)
• 3.8 Features of New Generation FPLDs(p. 50)
• 3.9 For additional information(p. 51)
• 3.10 Laboratory Exercises(p. 52)
• 4 Tutorial II: Sequential Design and Hierarchy(p. 54)
• 4.1 Install the Tutorial Files and UP1core Library(p. 54)
• 4.2 Open the tutor2 Schematic(p. 54)
• 4.3 Browse the Hierarchy(p. 56)
• 4.4 Using Buses in a Schematic(p. 57)
• 4.5 Testing the Pushbutton Counter and Displays(p. 58)
• 4.6 Testing the Initial Design on the UP 1 Board(p. 59)
• 4.7 Fixing the Switch Contact Bounce Problem(p. 60)
• 4.8 Testing the Modified Design on the UP 1 Board(p. 61)
• 4.9 Laboratory Exercises(p. 61)
• 5 UP1core Library Functions(p. 66)
• 5.1 UP1core DEC_7SEG: Hex to Seven-segment Decoder(p. 67)
• 5.2 UP1core Debounce: Pushbutton Debounce(p. 68)
• 5.3 UP1core OnePulse: Pushbutton Single Pulse(p. 69)
• 5.4 UP1core Clk_Div: Clock Divider(p. 70)
• 5.5 UP1core VGA_Sync: VGA Video Sync Generation(p. 71)
• 5.6 UP1core CHAR_ROM: Character Generation ROM(p. 73)
• 5.7 UP1core Keyboard: Read Keyboard Scan Code(p. 74)
• 5.8 UP1core Mouse: Mouse Cursor(p. 75)
• 6 Using VHDL for Synthesis of Digital Hardware(p. 78)
• 6.1 VHDL Data Types(p. 78)
• 6.2 VHDL Operators(p. 79)
• 6.3 VHDL Based Synthesis of Digital Hardware(p. 80)
• 6.4 VHDL Synthesis Models of Gate Networks(p. 80)
• 6.5 VHDL Synthesis Model of a Seven-segment LED Decoder(p. 81)
• 6.6 VHDL Synthesis Model of a Multiplexer(p. 83)
• 6.7 VHDL Synthesis Model of Tri-State Output(p. 84)
• 6.8 VHDL Synthesis Models of Flip-flops and Registers(p. 84)
• 6.9 Accidental Synthesis of Inferred Latches(p. 86)
• 6.10 VHDL Synthesis Model of a Counter(p. 86)
• 6.11 VHDL Synthesis Model of a State Machine(p. 87)
• 6.12 VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifter(p. 89)
• 6.13 VHDL Synthesis of Multiply and Divide Hardware(p. 90)
• 6.14 VHDL Synthesis Models for Memory(p. 91)
• 6.15 Hierarchy in VHDL Synthesis Models(p. 94)
• 6.16 Using a Testbench for Verification(p. 96)
• 6.17 For additional information(p. 97)
• 6.18 Laboratory Exercises(p. 97)
• 7 State Machine Design: The Electric Train Controller(p. 102)
• 7.1 The Train Control Problem(p. 102)
• 7.2 Track Power (T1, T2, T3, and T4)(p. 104)
• 7.3 Track Direction (DA1-DA0, and DB1-DB0)(p. 104)
• 7.4 Switch Direction (SW1, SW2, and SW3)(p. 105)
• 7.5 Train Sensor Input Signals (S1, S2, S3, S4, and S5)(p. 105)
• 7.6 An Example Controller Design(p. 106)
• 7.7 VHDL Based Example Controller Design(p. 110)
• 7.8 Simulation Vector file for State Machine Simulation(p. 112)
• 7.9 Running the Train Control Simulation(p. 115)
• 7.10 Running the Video Train System (After Successful Simulation)(p. 116)
• 7.11 Laboratory Exercises(p. 117)
• 8 A Simple Computer Design: The [mu]P 1(p. 122)
• 8.1 Computer Programs and Instructions(p. 123)
• 8.2 The Processor Fetch, Decode and Execute Cycle(p. 124)
• 8.3 VHDL Model of the [mu]P 1(p. 131)
• 8.4 Simulation of the [mu]P1 Computer(p. 134)
• 8.5 Laboratory Exercises(p. 135)
• 9 VGA Video Display Generation(p. 140)
• 9.1 Video Display Technology(p. 140)
• 9.2 Video Refresh(p. 140)
• 9.3 Using a CPLD for VGA Video Signal Generation(p. 143)
• 9.4 A VHDL Sync Generation Example: UP1core VGA_SYNC(p. 144)
• 9.5 Final Output Register for Video Signals(p. 146)
• 9.6 Required Pin Assignments for Video Output(p. 146)
• 9.7 Video Examples(p. 147)
• 9.8 A Character Based Video Design(p. 147)
• 9.9 Character Selection and Fonts(p. 148)
• 9.10 VHDL Character Display Design Examples(p. 151)
• 9.11 A Graphics Memory Design Example(p. 153)
• 9.12 Video Data Compression(p. 154)
• 9.13 Video Color Mixing using Dithering(p. 155)
• 9.14 VHDL Graphics Display Design Example(p. 155)
• 9.15 Laboratory Exercises(p. 157)
• 10 Communications: Interfacing to the PS/2 Keyboard(p. 160)
• 10.1 PS/2 Port Connections(p. 160)
• 10.2 Keyboard Scan Codes(p. 161)
• 10.3 Make and Break Codes(p. 161)
• 10.4 The PS/2 Serial Data Transmission Protocol(p. 161)
• 10.5 Scan Code Set 2 for the PS/2 Keyboard(p. 164)
• 10.6 The Keyboard UP1core(p. 166)
• 10.7 A Design Example Using the Keyboard UP1core(p. 169)
• 10.8 For Additional Information(p. 170)
• 10.9 Laboratory Exercises(p. 170)
• 11 Communications: Interfacing to the PS/2 Mouse(p. 172)
• 11.1 The Mouse UP1core(p. 174)
• 11.2 Mouse Initialization(p. 174)
• 11.3 Mouse Data Packet Processing(p. 175)
• 11.4 An Example Design Using the Mouse UP1core(p. 176)
• 11.5 For Additional Information(p. 176)
• 11.6 Laboratory Exercises(p. 176)
• 12 Robotics: The UP1-bot(p. 178)
• 12.1 The UP1-bot Design(p. 178)
• 12.2 UP1-bot Servo Drive Motors(p. 178)
• 12.3 Modifying the Servos to make Drive Motors(p. 179)
• 12.4 VHDL Servo Driver Code for the UP1-bot(p. 180)
• 12.5 Sensors for the UP1-bot(p. 182)
• 12.6 Assembly of the UP1-bot Body(p. 190)
• 12.7 UP1-bot FLEX Expansion B Header Pins(p. 197)
• 12.8 An Alternative UP 1 Robot Project Based on an R/C Car(p. 198)
• 12.9 For Additional Information(p. 203)
• 12.10 Laboratory Exercises(p. 204)
• 13 A RISC Design: Synthesis of the MIPS Processor Core(p. 210)
• 13.1 The MIPS Instruction Set and Processor(p. 210)
• 13.2 Using VHDL to Synthesize the MIPS Processor Core(p. 213)
• 13.3 The Top-Level Module(p. 214)
• 13.4 The Control Unit(p. 217)
• 13.5 The Instruction Fetch Stage(p. 219)
• 13.6 The Decode Stage(p. 222)
• 13.7 The Execute Stage(p. 224)
• 13.8 The Data Memory Stage(p. 226)
• 13.9 Simulation of the MIPS Design(p. 227)
• 13.10 MIPS Hardware Implementation on the UP 1 or UP 1X Board(p. 228)
• 13.11 For Additional Information(p. 229)
• 13.12 Laboratory Exercises(p. 230)
• Appendix A Generation of Pseudo Random Binary Sequences(p. 235)
• Appendix B MAX+PLUS II Design and Data File Extensions(p. 237)
• Appendix C UP 1 and UP 1X Pin Assignments(p. 239)
• Appendix D The Wintim Meta Assembler(p. 243)
• Appendix E An Introduction to Verilog for VHDL users(p. 252)
• Glossary(p. 259)
• Index(p. 267)
• About the Accompanying CD-ROM(p. 270)