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Digital phase lock loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others.Digital Phase Lock Loopsthen illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. The practical real-time results, of the various TDTL architectures, obtained from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.

Tabla de contenidos provista por Syndetics

• Preface(p. xi)
• Acknowledgement(p. xv)
• Acronyms(p. xvii)
• 1 General Review of Phase-Locked Loops(p. 1)
• 1.1 Overview of Phase-Locked Synchronization Schemes(p. 1)
• 1.2 The Synchronization Challenge(p. 3)
• 1.3 Phase-Locked Loops(p. 4)
• 1.3.1 Analog Phase-locked Loops(p. 4)
• 1.3.2 PLL Basic Components(p. 6)
• 1.3.3 PLL analysis(p. 10)
• 1.4 Conclusions(p. 13)
• 2 Digital Phase Lock Loops(p. 15)
• 2.1 Introduction(p. 15)
• 2.2 Classification of DPLLs(p. 16)
• 2.3 Conclusions(p. 30)
• 3 The Time-Delay Digital Tanlock Loops (TDTLs)(p. 31)
• 3.1 Introduction(p. 31)
• 3.2 Structure and System Equation(p. 32)
• 3.2.1 Structure of the TDTL(p. 32)
• 3.2.2 System Equation(p. 32)
• 3.2.3 The Characteristic Function(p. 34)
• 3.3 System Analysis(p. 35)
• 3.3.1 First-order TDTL(p. 35)
• 3.3.2 Second-Order TDTL(p. 43)
• 3.4 Locking Speed(p. 45)
• 3.4.1 Convergence of the First-Order TDTL(p. 46)
• 3.5 Conclusions(p. 48)
• 4 Hilbert Transformer and Time-Delay(p. 51)
• 4.1 Introduction(p. 51)
• 4.2 Statistical Behavior of HT and Time-Delay in i.i.d. Additive Gaussian Noise(p. 53)
• 4.2.1 Input-Output Relationships in the Presence of Noise(p. 53)
• 4.2.2 Joint PDF of the Amplitude and Phase Random Variables(p. 54)
• 4.2.3 PDF of the Phase Random Variable(p. 56)
• 4.2.4 PDF of the Phase Noise(p. 57)
• 4.2.5 Expectation and Variance of the Phase Noise(p. 58)
• 4.2.6 The phase Estimator and Ranges of Cramer-Rao Bounds(p. 62)
• 4.2.7 A Symmetric Transformation(p. 65)
• 4.3 Conclusions(p. 66)
• 5 The Time-delay Digital Tanlock Loop in Noise(p. 69)
• 5.1 Introduction(p. 69)
• 5.2 Noise Analysis of the TDTL(p. 70)
• 5.2.1 System Equation(p. 70)
• 5.2.2 Statistical Behavior of TDTL Phase Error Detector(p. 71)
• 5.2.3 Phase Estimation and Cramer-Rao Bounds(p. 74)
• 5.2.4 Statistical Behavior of the TDTL in Gaussian Noise(p. 77)
• 5.3 Conclusions(p. 81)
• 6 Architectures for Improved Performance(p. 85)
• 6.1 Introduction(p. 85)
• 6.2 Simulation Results of First-Order TDTL(p. 85)
• 6.3 Improved First-Order TDTL Architectures(p. 88)
• 6.3.1 Delay Switching Architecture(p. 89)
• 6.3.2 Adaptive Gain Architecture(p. 94)
• 6.3.3 Combined Delay Switching and Adaptive Gain(p. 100)
• 6.3.4 Sample Sensing Adaptive Architecture(p. 105)
• 6.3.5 Early Error Sensing Adaptive Architecture(p. 113)
• 6.4 Simulation Results of Second-Order TDTL(p. 115)
• 6.5 Improved Second-Order TDTL Architectures(p. 121)
• 6.5.1 Adaptive Filter Coefficients Second-Order TDTL(p. 121)
• 6.5.2 Adaptive Loop Gain Second-Order TDTL(p. 123)
• 6.6 A Variable Order TDTL Architecture(p. 123)
• 6.7 Conclusions(p. 134)
• 7 FPGA Reconfigurable TDTL(p. 137)
• 7.1 Overview of Reconfigurable Systems(p. 137)
• 7.2 FPGA Structure and Operation(p. 138)
• 7.3 Xtreme DSP Development System(p. 142)
• 7.4 TDTL FPGA Implementation(p. 149)
• 7.4.1 The CORDIC Arctangent Block(p. 151)
• 7.4.2 The Digital Controlled Oscillator(p. 152)
• 7.4.3 The CORDIC Divider(p. 154)
• 7.5 Real-Time TDTL Results(p. 156)
• 7.5.1 First-Order TDTL(p. 157)
• 7.5.2 Second-Order TDTL(p. 157)
• 7.5.3 Sample Sensing Adaptive TDTL(p. 159)
• 7.6 Conclusions(p. 161)
• 8 Selected Applications(p. 165)
• 8.1 PM Demodulation Using TDTL(p. 165)
• 8.2 Performance in Gaussian Noise(p. 169)
• 8.3 Simulation Results(p. 171)
• 8.4 FSK and FM Demodulation(p. 172)
• 8.5 Wideband FM Signal Detection(p. 173)
• 8.6 Conclusions(p. 176)
• Bibliography(p. 179)
• Index(p. 189)

Notas de autor provistas por Syndetics

Prof. Al-Araji received the B.Sc., M.Sc., and Ph.D. degrees from the University of Wales Swansea, (UK), all in electrical engineering in 1968, 1969, and 1972 respectively. Since September 2002, Professor Al-Araji was appointed Professor and Head of Communications Engineering Department at Etisalat University College (Emirates Telecommunication Cooperation), Sharjah, UAE. Prior to that and for six years he was working at the Transmission Network Systems, Scientific-Atlanta, Atlanta, Georgia, USA as Senior Staff Electrical Engineer. During the academic year 1995/1996, Prof. Al-Araji was visiting professor at the Ohio State University, Columbus, Ohio, USA. He was visiting professor at King's College, University of London, England, during the summers of 1988 and 1989. Prof. Al-Araji was professor and Department Head at the University of Baghdad, Iraq, and the University of Yarmouk, Jordan.

Prof. Al-Araji was awarded the British IERE Clerk Maxwell Premium for a paper published in 1976 and the Scientific-Atlanta award for outstanding achievement in the year 2000. He was an Iraqi National member of URSI Commissions C and D, and the ITU (CCIR Group 8). His research interests include synchronization techniques, communication signal processing, and CATV systems and networks. He has published over 50 papers in international Journals and Conferences and holds 6 US Patents and one International Patent. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Prof. Al-Araji is a senior member of the IEEE. His e-mail address is: alarajis@euc.ac.ae.