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KEY BENEFIT : Learn the fundamentals of processor and computer design from the newest edition of this award winning text. KEY TOPICS : Introduction; Computer Evolution and Performance; A Top-Level View of Computer Function and Interconnection; Cache Memory; Internal Memory Technology; External Memory; I/O; Operating System Support; Computer Arithmetic; Instruction Sets: Characteristics and Functions; Instruction Sets: Addressing Modes and Formats; CPU Structure and Function; RISCs; Instruction-Level Parallelism and Superscalar Processors; Control Unit Operation; Microprogrammed Control; Parallel Processing; Multicore Architecture. Online Chapters: Number Systems; Digital Logic; Assembly Language, Assemblers, and Compilers; The IA-64 Architecture. MARKET : Ideal for professionals in computer science, computer engineering, and electrical engineering.

Tabla de contenidos provista por Syndetics

• Web Site for the Book(p. iv)
• About the Author(p. xi)
• Preface(p. xiii)
• Chapter 0 Reader's Guide(p. 1)
• 0.1 Outline of the Book(p. 2)
• 0.2 A Roadmap for Readers and Instructors(p. 2)
• 0.3 Why Study Computer Organization and Architecture(p. 3)
• 0.4 Internet and Web Resources(p. 4)
• Part 1 Overview(p. 7)
• Chapter 1 Introduction(p. 8)
• 1.1 Organization and Architecture(p. 9)
• 1.2 Structure and Function(p. 10)
• 1.3 Key Terms and Review Questions(p. 15)
• Chapter 2 Computer Evolution and Performance(p. 16)
• 2.1 A Brief History of Computers(p. 17)
• 2.2 Designing for Performance(p. 38)
• 2.3 The Evolution of the Intel x86 Architecture(p. 44)
• 2.4 Embedded Systems and the ARM(p. 46)
• 2.5 Performance Assessment(p. 50)
• 2.6 Recommended Reading and Web Sites(p. 57)
• 2.7 Key Terms, Review Questions, and Problems(p. 59)
• Part 2 The Computer System(p. 63)
• Chapter 3 A Top-Level View of Computer Function and Interconnection(p. 65)
• 3.1 Computer Components(p. 66)
• 3.2 Computer Function(p. 68)
• 3.3 Interconnection Structures(p. 83)
• 3.4 Bus Interconnection(p. 85)
• 3.5 PCI(p. 95)
• 3.6 Recommended Reading and Web Sites(p. 104)
• 3.7 Key Terms, Review Questions, and Problems(p. 104)
• Appendix 3A Timing Diagrams(p. 108)
• Chapter 4 Cache Memory(p. 110)
• 4.1 Computer Memory System Overview(p. 111)
• 4.2 Cache Memory Principles(p. 118)
• 4.3 Elements of Cache Design(p. 121)
• 4.4 Pentium 4 Cache Organization(p. 140)
• 4.5 ARM Cache Organization(p. 143)
• 4.6 Recommended Reading(p. 145)
• 4.7 Key Terms, Review Questions, and Problems(p. 146)
• Appendix 4A Performance Characteristics of Two-Level Memories(p. 151)
• Chapter 5 Internal Memory Technology(p. 158)
• 5.1 Semiconductor Main Memory(p. 159)
• 5.2 Error Correction(p. 169)
• 5.3 Advanced DRAM Organization(p. 173)
• 5.4 Recommended Reading and Web Sites(p. 179)
• 5.5 Key Terms, Review Questions, and Problems(p. 180)
• Chapter 6 External Memory(p. 184)
• 6.1 Magnetic Disk(p. 185)
• 6.2 RAID(p. 194)
• 6.3 Optical Memory(p. 203)
• 6.4 Magnetic Tape(p. 210)
• 6.5 Recommended Reading and Web Sites(p. 212)
• 6.6 Key Terms, Review Questions, and Problems(p. 214)
• Chapter 7 Input/Output(p. 217)
• 7.1 External Devices(p. 219)
• 7.2 I/O Modules(p. 222)
• 7.3 Programmed I/O(p. 224)
• 7.4 Interrupt-Driven I/O(p. 228)
• 7.5 Direct Memory Access(p. 236)
• 7.6 I/O Channels and Processors(p. 242)
• 7.7 The External Interface: Fire Wire and Infiniband(p. 244)
• 7.8 Recommended Reading and Web Sites(p. 253)
• 7.9 Key Terms, Review Questions, and Problems(p. 254)
• Chapter 8 Operating System Support(p. 259)
• 8.1 Operating System Overview(p. 260)
• 8.2 Scheduling(p. 271)
• 8.3 Memory Management(p. 277)
• 8.4 Pentium Memory Management(p. 288)
• 8.5 ARM Memory Management(p. 293)
• 8.6 Recommended Reading and Web Sites(p. 298)
• 8.7 Key Terms, Review Questions, and Problems(p. 299)
• Part 3 The Central Processing Unit(p. 303)
• Chapter 9 Computer Arithmetic(p. 305)
• 9.1 The Arithmetic and Logic Unit (ALU)(p. 306)
• 9.2 Integer Representation(p. 307)
• 9.3 Integer Arithmetic(p. 312)
• 9.4 Floating-Point Representation(p. 327)
• 9.5 Floating-Point Arithmetic(p. 334)
• 9.6 Recommended Reading and Web Sites(p. 342)
• 9.7 Key Terms, Review Questions, and Problems(p. 344)
• Chapter 10 Instruction Sets: Characteristics and Functions(p. 348)
• 10.1 Machine Instruction Characteristics and Functions(p. 348)
• 10.2 Types of Operands(p. 356)
• 10.3 Intel x86 and ARM Data Types(p. 358)
• 10.4 Types of Operations(p. 362)
• 10.5 Intel x86 and ARM Operation Types(p. 374)
• 10.6 Recommended Reading(p. 384)
• 10.7 Key Terms, Review Questions, and Problems(p. 385)
• Appendix 10A Stacks(p. 390)
• Appendix 10B Little, Big, and Bi-Endian(p. 396)
• Chapter 11 Instruction Sets: Addressing Modes and Formats(p. 400)
• 11.1 Addressing(p. 401)
• 11.2 x86 and ARM Addressing Modes(p. 408)
• 11.3 Instruction Formats(p. 413)
• 11.4 x86 and ARM Instruction Formats(p. 421)
• 11.5 Assembly Language(p. 426)
• 11.6 Recommended Reading(p. 428)
• 11.7 Key Terms, Review Questions, and Problems(p. 428)
• Chapter 12 Processor Structure and Function(p. 432)
• 12.1 Processor Organization(p. 433)
• 12.2 Register Organization(p. 435)
• 12.3 The Instruction Cycle(p. 440)
• 12.4 Instruction Pipelining(p. 444)
• 12.5 The x86 Processor Family(p. 461)
• 12.6 The ARM Processor(p. 469)
• 12.7 Recommended Reading(p. 475)
• 12.8 Key Terms, Review Questions, and Problems(p. 476)
• Chapter 13 Reduced Instruction Set Computers (RISCs)(p. 480)
• 13.1 Instruction Execution Characteristics(p. 482)
• 13.2 The Use of a Large Register File(p. 487)
• 13.3 Compiler-Based Register Optimization(p. 492)
• 13.4 Reduced Instruction Set Architecture(p. 494)
• 13.5 RISC Pipelining(p. 500)
• 13.6 MIPS R4000(p. 504)
• 13.7 SPARC(p. 511)
• 13.8 The RISC versus CISC Controversy(p. 517)
• 13.9 Recommended Reading(p. 518)
• 13.10 Key Terms, Review Questions, and Problems(p. 518)
• Chapter 14 Instruction-Level Parallelism and Superscalar Processors(p. 522)
• 14.1 Overview(p. 524)
• 14.2 Design Issues(p. 528)
• 14.3 Pentium 4(p. 538)
• 14.4 ARM Cortex-A8(p. 544)
• 14.5 Recommended Reading(p. 552)
• 14.6 Key Terms, Review Questions, and Problems(p. 554)
• Part 4 The Control Unit(p. 559)
• Chapter 15 Control Unit Operation(p. 561)
• 15.1 Micro-operations(p. 563)
• 15.2 Control of the Processor(p. 569)
• 15.3 Hardwired Implementation(p. 581)
• 15.4 Recommended Reading(p. 584)
• 15.5 Key Terms, Review Questions, and Problems(p. 584)
• Chapter 16 Microprogrammed Control(p. 586)
• 16.1 Basic Concepts(p. 587)
• 16.2 Microinstruction Sequencing(p. 596)
• 16.3 Microinstruction Execution(p. 602)
• 16.4 TI 8800(p. 614)
• 16.5 Recommended Reading(p. 624)
• 16.6 Key Terms, Review Questions, and Problems(p. 625)
• Part 5 Parallel Organization(p. 627)
• Chapter 17 Parallel Processing(p. 628)
• 17.1 The Use of Multiple Processors(p. 630)
• 17.2 Symmetric Multiprocessors(p. 632)
• 17.3 Cache Coherence and the MESI Protocol(p. 640)
• 17.4 Multithreading and Chip Multiprocessors(p. 646)
• 17.5 Clusters(p. 653)
• 17.6 Nonuniform Memory Access Computers(p. 660)
• 17.7 Vector Computation(p. 664)
• 17.8 Recommended Reading and Web Sites(p. 676)
• 17.9 Key Terms, Review Questions, and Problems(p. 677)
• Chapter 18 Multicore Computers(p. 684)
• 18.1 Hardware Performance Issues(p. 685)
• 18.2 Software Performance Issues(p. 690)
• 18.3 Multicore Organization(p. 694)
• 18.4 Intel x86 Multicore Organization(p. 696)
• 18.5 ARM11 MPCore(p. 699)
• 18.6 Recommended Reading and Web Sites(p. 704)
• 18.7 Key Terms, Review Questions, and Problems(p. 705)
• Appendix A Projects for Teaching Computer Organization and Architecture(p. 707)
• A.1 Interactive Simulations(p. 708)
• A.2 Research Projects(p. 708)
• A.3 Simulation Projects(p. 710)
• A.4 Assembly Language Projects(p. 711)
• A.5 Reading/Report Assignments(p. 711)
• A.6 Writing Assignments(p. 712)
• A.7 Test Bank(p. 712)
• Appendix B Assembly Language and Related Topics(p. 713)
• B.1 Assembly Language(p. 714)
• B.2 Assemblers(p. 723)
• B.3 Loading and Linking(p. 728)
• B.4 Recommended Reading and Web Sites(p. 735)
• B.5 Key Terms, Review Questions, and Problems(p. 736)
• Online Chapters WilliamStalling.com/COA/COA8e.html
• Chapter 19 Number Systems 19-1
• 19.1 The Decimal System 19-2
• 19.2 The Binary System 19-2
• 19.3 Converting between Binary and Decimal 19-3
• 19.4 Hexadecimal Notation 19-5
• 19.5 Key Terms, Review Questions, and Problems 19-8
• Chapter 20 Digital Logic 20-1
• 20.1 Boolean Algebra 20-2
• 20.2 Gates 20-4
• 20.3 Combinational Circuits 20-7
• 20.4 Sequential Circuits 20-24
• 20.5 Programmable Logic Devices 20-33
• 20.6 Recommended Reading and Web Site 20-38
• 20.7 Key Terms and Problems 20-39
• Chapter 21 The IA-64 Architecture 21-1
• 21.1 Motivation 21-3
• 21.2 General Organization 21-4
• 21.3 Predication, Speculation, and Software Pipelining 21-6
• 21.4 IA-64 Instruction Set Architecture 21-23
• 21.5 Itanium Organization 21-28
• 21.6 Recommended Reading and Web Sites 21-31
• 21.7 Key Terms, Review Questions, and Problems 21-32
• Online Appendices William Stallings.com/COA/COA8e.html
• Appendix C Hash Tables
• Appendix D Victim Cache Strategies
• D.1 Victim Cache
• D.2 Selective Victim Cache
• Appendix E Interleaved Memory
• Appendix F International Reference Alphabet
• Appendix G Virtual Memory Page Replacement Algorithms
• Appendix H Recursive Procedures
• H.1 Recursion
• H.2 Activation Tree Representation
• H.3 Stack Processing
• H.4 Recursion and Iteration
• Appendix I Additional Instruction Pipeline Topics
• I.1 Pipeline Reservation Tables
• I.2 Reorder Buffers
• I.3 Scoreboarding
• I.4 Tomasulo's Algorithm
• Appendix J Linear Tape Open Technology
• Appendix K DDR SDRAM
• Glossary(p. 740)
• References(p. 750)
• Index(p. 763)

Notas de autor provistas por Syndetics

William Stallings has made a unique contribution to understanding the broad sweep of technical developments in computer networking and computer architecture. He has authored 18 titles, and counting revised editions, a total of 35 books on various aspects of these subjects. In over 20 years in the field, he has been a technical contributor, technical manager, and an executive with several high-technology firms. Currently he is an independent consultant whose clients have included computer and networking manufacturers and customers, software development firms, and leading-edge government research institutions.

He has six times received the prize for best Computer Science and Engineering textbook of the year from the Textbook and Academic Authors Association.

Bill has designed and implemented both TCP/IP-based and OSI-based protocol suites on a variety of computers and operating systems, ranging from microcomputers to mainframes. As a consultant, he has advised government agencies, computer and software vendors, and major users on the design, selection, and use of networking software and products.

Dr. Stallings holds a Ph.D. from M.I.T. in Computer Science and a B.S. from Notre Dame in Electrical Engineering.